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tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 3-v to 6-v input, 1.5-a output synchronous-buck pwm switcher with integrated fets ( swift ? ) check for samples: tps54110 1 features description 2 ? integrated mosfet switches for high as members of the swift family of dc/dc regulators, efficiency at 1.5-a continuous output source the tps54110 low-input-voltage high-output-current or sink current synchronous-buck pwm converter integrates all required active components. included on the ? 0.9-v to 3.3-v adjustable output voltage with substrate with the listed features are a true, high- 1% accuracy performance, voltage error amplifier that provides ? externally compensated for design flexibility high performance under transient conditions; an ? fast transient response undervoltage-lockout circuit to prevent start-up until the input voltage reaches 3 v; an internally and ? wide pwm frequency: fixed 350 khz, 550 khz, externally set slow-start circuit to limit in-rush or adjustable 280 khz to 700 khz currents; and a power-good output useful for ? load protected by peak current limit and processor/logic reset, fault signaling, and supply thermal shutdown sequencing. ? integrated solution reduces board area and the tps54110 device is available in a thermally total cost enhanced 20-pin tssop (pwp) powerpad ? package, which eliminates bulky heatsinks. ti applications provides evaluation modules and the swift designer software tool to aid in quickly achieving high- ? low-voltage, high-density systems with performance power supply designs to meet power distributed at 5 v or 3.3 v aggressive equipment development cycles. ? point of load regulation for high performance dsps, fpgas, asics, and microprocessors ? broadband, networking, and optical communications infrastructure ? portable computing/notebook pcs 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 swift, powerpad are trademarks of texas instruments. production data information is current as of publication date. ? 2003 C 2011, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. (6,3 mm x 6,4 mm) typical size vin ph tps54110 boot pgnd comp vsense agnd vbias compensationnetwork input output 50 55 60 65 70 75 80 85 90 95 100 0 0.25 0 . 5 0 . 75 1 1.25 1 . 5 i o output current a efficiency % efficiency vs output current 100 f 2200 pf 0.047 f 0.1 f 10 f 3.92 k 2.05 k 3.92 k 19.1 k 6.8 h 2700 pf 33 pf simplified schematic .
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. ordering information packaged devices t j output voltage plastic htssop (pwp) (1) C 40 c to 125 c adjustable to 0.891 v tps54110pwp (1) the pwp package is also available taped and reeled. add an r suffix to the device type (i.e., tps54110pwpr). see application section of data sheet for powerpad drawing and layout information. absolute maximum ratings over operating free-air temperature range unless otherwise noted (1) value unit vin, ss/ena, sync C 0.3 to 7 v rt C 0.3 to 6 v input voltage range, v i vsense C 0.3 to 4 v boot C 0.3 to 17 v vbias, pwrgd, comp C 0.3 to 7 v output voltage range, v o ph C 0.6 to 10 v ph internally limited source current, i o comp, vbias 6 ma ph 3.5 a sink current comp 6 ma ss/ena,pwrgd 10 ma voltage differential agnd to pgnd 0.3 v continuous power dissipation see thermal information table operating virtual junction temperature range, t j C 40 to 150 c storage temperature, t stg C 65 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions min nom max unit input voltage range, v i 3 6 v operating junction temperature, t j C 40 125 c thermal information tps54110 thermal metric (1) pwp units 20 pins ja junction-to-ambient thermal resistance 34.0 jctop junction-to-case (top) thermal resistance 21.2 jb junction-to-board thermal resistance 6.7 c/w jt junction-to-top characterization parameter 0.3 jb junction-to-board characterization parameter 6.5 jcbot junction-to-case (bottom) thermal resistance 1.5 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . 2 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110
tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 electrical characteristics t j = C 40 c to 125 c, vin = 3 v to 6 v (unless otherwise noted) parameter test conditions min typ max unit supply voltage, vin vin input voltage range 3 6 v f s = 350 khz, sync 0.8 v, rt open 4.5 8.5 f s = 550 khz, phase pin open, quiescent current 5.8 9.6 ma sync 2.5 v, rt open, shutdown, ss/ena = 0 v 1 1.4 under voltage lock out start threshold voltage, uvlo 2.95 3 v stop threshold voltage, uvlo 2.70 2.80 hysteresis voltage, uvlo 0.12 v rising and falling edge deglitch, 2.5 s uvlo (1) bias voltage output voltage, vbias i (vbias) = 0 2.70 2.80 2.90 v v o output current, vbias (2) 100 a cumulative reference v ref accuracy 0.882 0.891 0.900 v regulation i l = 0.75 a, f s = 350 khz, t j = 85 c 0.05 line regulation (1) (3) %/v i l = 0.75 a, f s = 550 khz, t j = 85 c 0.05 i l = 0 a to 1.5 a, f s = 350 khz, t j = 85 c 0.01 load regulation (1) (3) %/a i l = 0 a to 1.5 a f s = 550 khz, t j = 85 c 0.01 oscillator sync 0.8 v, rt open 280 350 420 internally set free-running khz frequency range sync 2.5 v, rt open 440 550 660 rt = 180 k (1% resistor to agnd) (1) 252 280 308 externally set free-running rt = 100 k (1% resistor to agnd) 460 500 540 khz frequency range rt = 68 k (1% resistor to agnd) (1) 663 700 762 high-level threshold voltage, 2.5 v sync low-level threshold voltage, 0.8 v sync pulse duration, sync (1) 50 ns frequency range, sync (1) 330 700 khz ramp valley (1) 0.75 v ramp amplitude (peak-to-peak) (1) 1 v minimum controllable on time (1) 200 ns maximum duty cycle 90 % (1) specified by design (2) static resistive loads only (3) specified by the circuit used in figure 9 . ? 2003 C 2011, texas instruments incorporated submit documentation feedback 3 product folder link(s): tps54110
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com electrical characteristics (continued) t j = C 40 c to 125 c, vin = 3 v to 6 v (unless otherwise noted) parameter test conditions min typ max unit error amplifier error-amplifier open loop voltage 1 k comp to agnd (4) 90 110 db gain error-amplifier unity gain parallel 10 k , 160 pf comp to agnd (4) 3 5 mhz bandwidth error-amplifier common-mode powered by internal ldo (4) 0 vbias v input voltage range i ib input bias current, vsense vsense = v ref 60 250 na output voltage slew rate v o 1.2 v/ s (symmetric), comp (4) pwm comparator pwm comparator propagation delay time, pwm comparator 10 mv overdrive (4) 70 85 ns input to ph pin (excluding dead time) slow-start/enable enable threshold voltage, 0.82 1.20 1.40 v ss/ena enable hysteresis voltage, 0.03 v ss/ena (4) falling-edge deglitch, ss/ena (4) 2.5 s internal slow-start time 2.6 3.35 4.1 ms charge current, ss/ena ss/ena = 0 v 3 5 8 a discharge current, ss/ena ss/ena = 1.3 v, v i = 1.5 v 1.5 2.3 4 ma power good power-good threshold voltage vsense falling 93 %v ref power-good hysteresis voltage (4) 3 %v ref power-good falling-edge 35 s deglitch (4) output saturation voltage, i (sink) = 2.5 ma 0.18 0.30 v pwrgd leakage current, pwrgd v i = 5.5 v 1 a current limit v i = 3 v, output shorted (4) 3.0 current limit trip point a v i = 6 v, output shorted (4) 3.5 current-limit leading edge 100 ns blanking time current-limit total response time 200 ns thermal shutdown thermal-shutdown trip point (4) 135 150 165 c thermal-shutdown hysteresis (4) 10 c output power mosfets i o = 1.5 a, v i = 6 v (6) 240 480 r ds(on) power mosfet switches (5) m i o = 1.5 a, v i = 3 v (6) 345 690 (4) specified by design (5) includes package and bondwire resistance (6) matched mosfets, low side r ds(on) production tested, high side r ds(on) specified by design 4 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110
tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 pin assignments pwp package (top view) terminal functions terminal description name no. agnd 1 analog ground internally connected to the sensitive analog-ground circuitry. connect to pgnd and powerpad. bootstrap input. 0.022- f to 0.1- f low-esr capacitor connected from boot to ph generates floating drive for the boot 5 high-side fet driver. comp 3 error amplifier output. connect compensation network from comp to vsense. power ground. high current return for the low-side driver and power mosfet. connect pgnd with large copper pgnd 11 C 13 areas to the input and output supply returns, and negative terminals of the input and output capacitors. connect to agnd and powerpad. ph 6 C 10 phase input/output. junction of the internal high and low-side power mosfets, and output inductor. power-good open drain output. high when vsense 93% vref, otherwise pwrgd is low. note that output is low pwrgd 4 when ss/ena is low or internal shutdown signal active. rt 20 frequency setting resistor input. connect a resistor from rt to agnd to set the switching frequency, f s . slow-start/enable input/output. dual-function pin that provides logic input to enable/disable device operation and ss/ena 18 capacitor input to externally set the start-up time. synchronization input. dual-function pin that provides logic input to synchronize to an external oscillator or pin select sync 19 between two internally set switching frequencies. when used to synchronize to an external signal, a resistor must be connected to the rt pin. internal bias regulator output. supplies regulated voltage to internal circuitry. bypass vbias pin to agnd pin with a vbias 17 high quality, low esr 0.1- f to 1.0- f ceramic capacitor. input supply for the power mosfet switches and internal bias regulator. bypass vin pins to pgnd pins close to vin 14 C 16 device package with a high quality, low esr 1- f to 10- f ceramic capacitor. vsense 2 error amplifier inverting input. ? 2003 C 2011, texas instruments incorporated submit documentation feedback 5 product folder link(s): tps54110 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 11 agnd vsense comp pwrgd boot phph ph ph ph rt sync ss/ena vbias vin vin vin pgnd pgnd pgnd
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com functional block diagram 6 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110 falling edge deglitch enable comparator 1.2 v vin 2.95 v hysteresis: 0.03 v 2.5 s falling and rising edge deglitch 2.5 s vin uvlo comparator hysteresis: 0.16 v internal/external slow-start (internal slow-start time = 3.35 ms reference vref = 0.891 v - + error amplifier thermal shutdown 150c shutdown ss _dis pwm comparator osc leading edge blanking 100 ns rqs adaptive dead-time and control logic shutdown vin reg vbias vinboot vin ph c o pgnd pwrgd falling edge deglitch 35 s vsense shutdown 0.93 v ref hysteresis: 0.03 vref powergood comparator agnd vbias ilim comparator 3 - 6 v v o sync rt comp vsense ss/ena tps54110 l out
tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 typical characteristics internally set oscillator drain-source on-state drain-source on-state resistance resistance frequency vs vs vs junction temperature junction temperature junction temperature figure 1. figure 2. figure 3. externally set oscillator frequency voltage reference output voltage regulation vs vs vs junction temperature junction temperature input voltage figure 4. figure 5. figure 6. internal slow-start time error amplifier vs open loop response junction temperature figure 7. figure 8. ? 2003 C 2011, texas instruments incorporated submit documentation feedback 7 product folder link(s): tps54110 0.8850 0.8870 0.8890 0.8910 0.8930 0.8950 3 4 5 6 f s = 350 khz t a = 85 c v ? i input voltage ? v ? output v oltage regulation ? v v o t ? j junction temperature ? c 3.353.20 2.90 ?40 0 25 85 internal slow-start time ? ms 3.50 3.65 125 3.803.05 2.75 1 f ? frequency ? hz 6040 0 0 10 100 1k 10 k 00 k 1m gain ? db 80 100 140 10 m 120 20 ?20 phase ? degrees 0?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 ?200 r l = 10 k, c l = 160 pf, t a = 25 c phase gain 450 ?40 0 25 f ? internally set oscillator frequency ?khz 550 750 85 125 650350 250 t ? j junction temperature ? c sync 2.5 v sync 0.8 v 0 0.1 0.2 0.3 0.4 ?40 0 25 85 125 i o = 1.5 a v i = 5 v t ? j junction temperature ? c drain-source on-state resistance ? 0.1 0.2 0.3 0.4 0.5 0.6 ?40 0 25 85 125 0 i o = 1.5 a v i = 3.3 v t ? j junction temperature ? c drain-source on-state resistance ? 400 ?40 0 25 f ? externally set oscillator frequency ? khz 500 800 85 125 700300 200 t ? j junction temperature ? c 600 rt = 68 k rt = 100 k rt = 180 k 0.889 ?40 0 25 ? voltage reference ? v 0.895 85 125 0.8930.887 0.885 t ? j junction temperature ? c 0.891 v ref
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com application information figure 9 shows the schematic diagram for a typical tps54110 application. the tps54110 can provide up to 1.5 a of output current at a nominal output voltage of 3.3 v. for proper thermal performance, the exposed powerpad underneath the device must be soldered down to the printed-circuit board. figure 9. application schematic design procedure the following design procedure can be used to select component values for the tps54110. alternately, the swift designer software can be used to generate a complete design. the swift designer software uses an iterative design procedure to access a comprehensive database of components when generating a design. this section presents a simplified discussion of the design process. design parameters the required parameters to begin the design process and values for this design example are listed in table 1 . table 1. design parameters design parameter example value input voltage range 4.5 to 5.5 v output voltage 3.3 v input ripple voltage 100 mv output ripple voltage 30 mv output current rating 1.5 a operating frequency 700 khz as an additional constraint, the design is set up to be small size and low component height. switching frequency the switching frequency is set within the range of 280 khz to 700 khz by connecting a resistor from the rt pin to agnd. equation 1 is used to determine the proper rt value. (1) in this example, the timing-resistor value chosen for r4 is 71.5 k , setting the switching frequency to 700 khz. 8 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110 5 c3 + rtsync ss/ena vbias vin vin vin pgnd pgnd pgnd pwrpd agnd vsense comp pwrgd boot phph ph ph ph 2019 18 17 16 15 14 13 12 11 10 9 8 7 6 4 3 2 1 vin (4.5 ? 5.5 v) c1 10 f r7 10 k ! u2 tps54110pwp pwrgd r4 71.5 k ! c5 .047 f c4 0.1 f c9 10 f 21 0.047 f r3 19.1 k ! c7 33 pf c6 2700 pf c8 2200 pf r5 2.05 k ! r1 10.7 k ! r2 3.92 k ! 1 2 l1 6.8 h 3.3 v at 1.5 a c2 100 f s(khz) 100 500khz rt(k ) = | w
tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 alternately, the tps54110 can be set to preprogrammed switching frequencies of 350 khz or 550 khz by connecting pins rt and sync as shown in table 2 . table 2. design parameters frequency rt sync 350 khz float float or agnd 550 khz float 2.5 v input capacitors the tps54110 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. the minimum value for the decoupling capacitor, c9, is 10 uf. a high quality ceramic type x5r or x7r with a voltage rating greater than the maximum input voltage is recommended. a bulk input capacitor may be needed, especially if the tps54110 circuit is not located within approximately 2 inches from the input voltage source. the capacitance value is not critical, but the voltage rating must be greater than the maximum input voltage including ripple voltage. the capacitor must filter the input ripple voltage to acceptable levels. input ripple voltage can be approximated by equation 2 : (2) where iout(max) is the maximum load current, ? sw is the switching frequency, c bulk is the bulk capacitor value and esr max is the maximum series resistance of the bulk capacitor. worst-case rms ripple current is approximated by equation 3 : (3) in this case the input ripple voltage is 66 mv with a 10- f bulk capacitor. figure 15 shows the measured ripple waveform. the rms ripple current is 0.75 a. the maximum voltage across the input capacitors is v inmax + v in /2. the bypass capacitor and input bulk capacitor are each rated for 6.3 v and a ripple-current capacity of 1.5 a, providing some margin. it is very important that the maximum ratings for voltage and current are not exceeded under any circumstance. output filter components two components, l1 and c2, are selected for the output filter. since the tps54110 is an externally-compensated device, a wide range of filter-component types and values are supported. inductor selection use equation 4 to calculate the minimum value of the output inductor: (4) k ind is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. for designs using low-esr capacitors such as ceramics, use k ind = 0.2. when using higher esr output capacitors, k ind = 0.1 yields better results. if higher ripple currents can be tolerated, k ind can be increased allowing for a smaller output-inductor value. this example design uses k ind = 0.2, yielding a minimum inductor value of 6.29 h. the next-higher standard value of 6.8 h is chosen for this design. if a lower inductor value is desired, a larger amount of ripple current must be tolerated. the rms-current and saturation-current ratings of the output filter inductor must not be exceeded. the rms inductor current can be found from equation 5 : ? 2003 C 2011, texas instruments incorporated submit documentation feedback 9 product folder link(s): tps54110 ( ) d + 0.25 out(max) = in max out(max) bulk sw i v i esr c | out(max) cin i i 2 = ( ) f ) in(max out out min ind out in(max) sw v v -v l v k i =
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com (5) the peak inductor current is determined from equation 6 : (6) for this design, the rms inductor current is 1.503 a and the peak inductor current is 1.673 a. the inductor chosen is a coilcraft ds3316p-682 6.8 h. it has a saturationcurrent rating of 2.8 a and an rms current rating of 2.2 a, easily meeting these requirements. capacitor selection the important design parameters for the output capacitor are dc voltage, ripple current, and equivalent series resistance (esr). the dc-voltage and ripple-current ratings must not be exceeded. the esr rating is important because along with the inductor current it determines the output ripple voltage level. the actual value of the output capacitor is not critical, but some practical limits do exist. consider the relationship between the desired closed-loop crossover frequency of the design and lc corner frequency of the output filter. in general, it is desirable to keep the closed-loop crossover frequency at less than 1/5 of the switching frequency. with high switching frequencies such as the 700 khz frequency of this design, internal circuit limitations of the tps54110 limit the practical maximum crossover frequency to about 100 khz. to allow adequate phase gain in the compensation network, set the lc corner frequency to approximately one decade below the closed-loop crossover frequency. this limits the minimum capacitor value for the output filter to: (7) where k is the frequency multiplier for the spread between f lc and f co . k should be between 5 and 15, typically 10 for one decade of difference. for a desired crossover of 60 khz, k=10 and a 6.8 h inductor, the minimum value for the output capacitor is 100 f. the selected output capacitor must be rated for a voltage greater than the desired output voltage plus one half the ripple voltage. any derating factors must also be included. the maximum rms ripple current in the output capacitor is given by equation 8 : (8) where nc is the number of output capacitors in parallel. the maximum esr of the output capacitor is determined by the allowable output ripple specified in the initial design parameters. the output ripple voltage is the inductor ripple current times the esr of the output filter so the maximum specified esr as listed in the capacitor data sheet is given by equation 9 : (9) for this design example, a single 100 f output capacitor is chosen for c2. the calculated rms ripple current is 80 ma and the maximum esr required is 87 m . an example of a suitable capacitor is the sanyo poscap 6tpc100m, rated at 6.3 v with a maximum esr of 45 milliohms and a ripple-current rating of 1.7 a. other capacitor types work well with the tps54110, depending on the needs of the application. compensation components the external compensation used with the tps54110 allows for a wide range of output-filter configurations. a large range of capacitor values and dielectric types are supported. the design example uses type 3 compensation consisting of r1, r3, r5, c6, c7 and c8. additionally, r2 and r1 form a voltage-divider network that sets the output voltage. these component reference designators are the same as those used in the swift designer software. 10 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110 ) out in(max) out cout(rms) in(max) out sw c 1 v (v v i v l f n 12 - = ? ? ( ) ? ? d ? ? ? in(max) out sw max c p-p(max) out in(max) out v l f 0.8 esr =n v v v -v ( ) 2 1 12 2 out in(max) out l(rms) out(max) in(max) out sw v v v i i v l f 0.8 - ? ? = + ? ? out in(max) out l(pk) out(max) out in(max) sw v (v -v ) i i 1.6 v l f = + out min out co k c l 2 ( ) ? ? 1 = ? 2p| ?
tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 there are a number of different ways to design a compensation network. this procedure outlines a relatively simple procedure that produces good results with most output filter combinations. use the swift designer software for designs with unusually high closed-loop crossover frequencies; with low-value, low-esr output capacitors such as ceramics; or if you are unsure about the design procedure. a number of considerations apply when designing compensation networks for the tps54110. the compensated error-amplifier gain must not be limited by the open-loop amplifier gain characteristics and must not produce excessive gain at the switching frequency. also, the closed-loop crossover frequency must be set less than one fifth of the switching frequency, and the phase margin at crossover must be greater than 45 degrees. the general procedure outlined here meets these requirements without going into great detail about the theory of loop compensation. first, calculate the output filter lc corner frequency using equation 10 : (10) for the design example, ? lc = 6103 hz. choose a closed-loop crossover frequency greater than f lc and less than one fifth of the switching frequency. also, keep the crossover frequency below 100 khz, as the error amplifier may not provide the desired gain at higher frequencies. the 60-khz crossover frequency chosen for this design provides comparatively wide loop bandwidth while still allowing adequate phase boost to ensure stability. next, the values for the compensation components that set the poles and zeros of the compensation network are calculated. assuming an r1 value > than r5 and a c6 value > c7, the pole and zero locations are given by equation 11 through equation 14 : (11) (12) (13) (14) additionally there is a pole at the origin, which has unity gain at a frequency: (15) this pole is used to set the overall gain of the compensated error amplifier and determines the closed loop crossover frequency. since r1 is given as 10 k and the crossover frequency is selected as 60 khz, the desired f int is calculated from equation 16 : (16) and the value for c6 is given by equation 17 : (17) since c6 is calculated to be 2900 pf, and the location of the integrator crossover frequency is important in setting the overall loop crossover, adjust the value of r1 so that c6 is a standard value of 2700 pf, using equation 18 : (18) the value for r1 is 10.7 k ? 2003 C 2011, texas instruments incorporated submit documentation feedback 11 product folder link(s): tps54110 lc out out l c 1 | = 2p z r c 1 1 | = 2p 3 6 z r c 2 1 | = 2p 1 8 p r c 1 1 | = 2p 5 8 p r c 2 1 | = 2p 3 7 int r c 1 | = 2p 1 6 - co int 0.74 10 | | = 2 int c r 1 6 = 2p 1| lc r c 1 1 = 2p 6|
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com the first zero, f z1 is located at one half the output filter lc corner frequency, so r3 is calculated from: (19) the second zero, f z2 is located at the output filter lc corner frequency, so c8 is calculated from: (20) the first pole, f p1 is located to coincide with output filter esr zero frequency. this frequency is given by: (21) where r esr is the equivalent series resistance of the output capacitor. in this case, the esr zero frequency is 35.4 khz, and r5 is calculated from: (22) the final pole is placed at a frequency high enough above the closed-loop crossover frequency to avoid causing an excessive phase decrease at the crossover frequency while still providing enough attenuation so that there is little or no gain at the switching frequency. the f p2 pole location for this circuit is set to 4 times the closed-loop crossover frequency and the last compensation component value c7 is derived: (23) finally, calculate the r2 resistor value for the output voltage of 3.3 v using equation 24 : (24) for this tps54110 design, use r1 = 10.7 k instead of 10.0 k . r2 is then 3.92 k . since capacitors are only available in a limited range of standard values, the nearest standard value was chosen for each capacitor. the measured closed-loop response for this design is shown in figure 19 . bias and bootstrap capacitors every tps54110 design requires a bootstrap capacitor (c3), and a bias capacitor (c4). the bootstrap capacitor must be between 0.022 f and 0.1 f. this design uses 0.047 f. the bootstrap capacitor is located between the ph pins and boot. the bias capacitor is connected between the vbias pin and agnd. recommended values are 0.1 f to 1.0 f. this design uses 0.1 f. use high-quality ceramic capacitors with x7r or x5r grade dielectric for temperature stability. place them as close to the device pins as possible. grounding and powerpad layout the tps54110 has two internal grounds (analog and power). inside the tps54110, the analog ground connects all noise-sensitive signals, while the power ground connects the noisier power signals. the powerpad must be tied directly to agnd. noise injected between the two grounds can degrade the performance of the tps54110, particularly at higher output currents. however, ground noise on an analog ground plane can also cause problems with some of the control and bias signals. for these reasons, separate analog and power ground planes are recommended. tie these two planes together directly at the ic to reduce noise between the two grounds. the only components that tie directly to the power-ground plane are the input capacitor, the output capacitor, the input voltage decoupling capacitor, and the pgnd pins of the tps54110. the layout of the tps54110 evaluation module represents recommended layout for a 2-layer board. documentation for the tps54110 evaluation module is obtained from the texas instruments web site under the tps54110 product folder and in the application note, ti literature number slva109 . 12 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110 lc r c 1 3 = p 6| 1 8 = 2p 1| lc c r 0 1 | = 2p esr esr out r c 1 5 = 2p 8| esr r c co 8 r3 1 7 = p | c out r1 0.891 r2 v -0.891 =
tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 figure 10. recommended land pattern for 20-pin pwp powerpad layout considerations for thermal performance for operation at full rated load current, the analog ground plane must provide adequate heat dissipation area. a 3-inch-by-3-inch plane of 1-ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. most applications have larger areas of internal ground plane available. connect the powerpad to the largest area available. additional areas on the top or bottom layers also help dissipate heat. use any area available when 1.5-a or greater operation is desired. connect the exposed area of the powerpad to the analog ground-plane layer with 0.013-inch-diameter vias to avoid solder wicking through the vias. an adequate design includes six vias in the powerpad area with four additional vias located under the device package. the size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. additional vias in areas not under the device package enhance thermal performance. ? 2003 C 2011, texas instruments incorporated submit documentation feedback 13 product folder link(s): tps54110 minimum recommended exposed copper area for powerpad. 5mm stencils may require 10 percent larger area 0.2454 0.0150 0.06 0.0256 0.1700 0.1340 0.0620 0.0400 0.0400 0.0400 0.0600 0.0227 0.0600 0.1010 6 pl ? 0.0130 4 pl ? 0.0180 connect pin 1 to analog ground plane in this area for optimum performance minimum recommended top side analog ground area minimum recommended thermal vias: 6 .013 dia. inside powerpad area 4 .018 dia. under device as shown. additional .018 dia. vias may be used if top side analog ground area is extended. 0.2560
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com performance graphs all performance data shown for v i = 5 v, v o = 3.3 v, f s = 700 khz, t a = 25 c, figure 9 efficiency power dissipation load regulation vs vs vs output current output current output current figure 11. figure 12. figure 13. line regulation vs input voltage input voltage ripple output voltage ripple figure 14. figure 15. figure 16. output voltage transient response start up waveform measured loop response figure 17. figure 18. figure 19. 14 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110 v o = 10 mv/div (ac) v (phase) = 2 v/div time = 500 ns/div ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 4.5 4.75 5 5.2 5 5 .5 v ? i input voltage ? v output voltage varistion ? % i o = 1.5 a i o = 0.75 a i o = 0 a v o = 10 mv/div (ac) i o = 1 v/div time = 200 s/div v i = 2 v/div v o = 1 v/div time = 5 ms/div ?40 ?30 ?20 ?10 10 20 30 40 50 60 100 1 k 10 k 100 k 1 m ?180 ?150 ?120 ?90 ?60 ?30 0 30 60 90 120 150 180 gain phase f ? frequency ? hz 0 ?50 gain ? db ?60 phase ? degrees ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 0 0.25 0.5 0.75 1 1.25 1.5 output voltage varistion ? % i ? o output current ? a 50 55 60 65 70 75 80 85 90 95 100 0 0.25 0.5 0.75 1 1.25 1.5 i ? o output current ? a efficiency ? % 0 0.2 0.4 0.6 0.8 1 1.2 0 0.25 0.5 0.75 1 1.25 1.5 ? power dissipation ? w p d i o output current ? a ? v i = 50 mv/div (ac) v (phase) = 2 v/div time = 500 ns/div
tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 very-small form-factor application figure 20. small form-factor reference design figure 20 shows an application schematic for a tps54110 application designed for extremely small size. to achieve this goal, the design procedure given in the previous application circuit is modified. for example, in order to use a small-footprint coilcraft do3314-103mx inductor, the maximum-allowable inductor ripple current was increased above that normally specified. a small 0805 10- f ceramic capacitor is used in the output filter. all the additional components are 0402 case size. ? 2003 C 2011, texas instruments incorporated submit documentation feedback 15 product folder link(s): tps54110 5 c3 + rtsync ss/ena vbias vin vin vin pgnd pgnd pgnd pwrpd agnd vsense comp pwrgd boot phph ph ph ph 2019 18 17 16 15 14 13 12 11 10 9 8 7 6 4 3 2 1 vin c1 open r7 10 k u2 tps54110pwp pwrgd r4 71.5 k c5 open c4 0.1 f c9 10 f 21 0.047 f r3 1.74 k c7 47 pf c6 1000 pf c8 560 pf r5 432 r1 10.0 k r2 14.7 k 1 2 l1 1 h 1.5 v at 1.5 a c2 10 f
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com all performance data shown for v i = 5 v, v o = 1.5 v, f s = 700 khz, t a = 25 c, figure 20 efficiency power dissipation load regulation vs vs vs output current output current output current figure 21. figure 22. figure 23. line regulation vs input voltage input voltage ripple output voltage ripple figure 24. figure 25. figure 26. output voltage transient response start up waveform figure 27. figure 28. 16 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110 ?0.02 ?0.015 ?0.01 ?0.005 0.005 0.01 0.015 0.02 3 3.5 4 4.5 5 5.5 6 0 i o = 0 a i o = 0.75 a i o = 1.5 a v ? i input voltage ? v output voltage varistion ? % v o = 20 mv/div (ac) i o = 1 v/div time = 200 s/div v i = 1 v/div v o = 500 mv/div time = 5 ms/div 50 55 60 65 70 75 80 85 90 95 100 0 0.25 0.5 0.75 1 1.25 1.5 i ? o output current ? a efficiency ? % v i = 3.3 v v i = 5 v 0.2 0.4 0.6 0.8 1.2 0 0.25 0.5 0.75 1 1.25 1.5 ? power dissipation ? w p d i o output current ? a 0 1 v i = 3.3 v v i = 5 v ? ?0.1 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0.1 0 0 .2 5 0 . 5 0 .7 5 1 1.2 5 1. 5 output voltage varistion ? % i ? o output current ? a v i = 3.3 v v i = 5 v time = 500 ns/div v i = 50 mv/div (ac) v (phase) = 2 v/div v o = 20 mv/div (ac) v (phase) = 2 v/div time = 500 ns/div
tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 two-output sequenced-startup application figure 29. tps54110 sequencing application circuit in figure 29 , the power-good output of u1 is used as a sequencing signal in a two-output design. connecting the pwrgd pin of u1 to the ss/ena pin of u2 causes the 1.5-v output to ramp up after the 3.3-v output is within regulation. figure 30 shows the startup waveforms associated with this circuit. when v in reaches the uvlo-start threshold, the u1 output ramps up towards the 3.3-v set point. after the output reaches 90 percent of 3.3 v, the u1 asserts the power-good signal driving the u2 ss/ena input high. the output of u2 then ramps up towards the final output set point of 1.5 v. ? 2003 C 2011, texas instruments incorporated submit documentation feedback 17 product folder link(s): tps54110 6 45 c3 0.047 f 19 20 v i 5 v + c1 470 f pwrgd_3p3 r7 10 k u1 tps54110pwp r4 71.5 k c4 0.1 f c9 10 f 21 11 12 13 14 15 16 17 18 rt sync ss/ena vbias vin vin vin pgnd pgnd pgnd agnd vsense comp pwrgd boot ph ph ph phph pwpd r3 1.74 k c6 1000 pf c7 47 pf 10 9 8 7 6 5 4 3 2 1 c8 560 pf r5 432 r1 10 k r2 3.74 k l1 1 h 1 2 3.3 v at 1.5 a c14 0.047 f 19 20 pwrgd_1p5 r8 10 k u2 tps54110pwp r9 71.5 k c10 0.1 f c15 10 f 21 11 12 13 14 15 16 17 18 rt sync ss/ena vbias vin vin vin pgnd pgnd pgnd agnd vsense comp pwrgd boot ph ph ph phph pwpd r6 1.74 k c5 1000 pf c11 47 pf 10 9 8 7 3 2 1 c13 560 pf r12 432 r11 10 k r10 14.7 k l2 1 h 1 2 1.5 v at 1.5 a c2 10 f c12 10 f v out1 v out2
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com figure 30. sequencing start up waveforms 18 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110 v in ? 5 v/div u1 ? v out1 3.3 ? 2 v/div u1 pwrgd ? 5 v/div u2 ? v out2 1.5 ? 2 v/div
tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 detailed description under voltage lock out (uvlo) the tps54110 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage (vin) is insufficient. during power up, internal circuits are held inactive until vin exceeds the nominal uvlo threshold voltage of 2.95 v. once the uvlo start threshold is reached, device start-up begins. the device operates until vin falls below the nominal uvlo stop threshold of 2.8 v. hysteresis in the uvlo comparator, and a 2.5- s rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise on vin. slow-start/enable (ss/ena) the slow-start/enable pin provides two functions; first, the pin acts as an enable (shutdown) control by keeping the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 v. when ss/ena exceeds the enable threshold, device start up begins. the reference voltage fed to the error amplifier is linearly ramped up from 0 v to 0.891 v in 3.35 ms. similarly, the converter output voltage reaches regulation in approximately 3.35 ms. voltage hysteresis and a 2.5- s falling edge deglitch circuit reduce the likelihood of triggering the enable due to noise. the second function of the ss/ena pin provides an external means of extending the slow-start time with a low-value capacitor connected between ss/ena and agnd. adding a capacitor to the ss/ena pin has two effects on start-up. first, a delay occurs between release of the ss/ena pin and start up of the output. the delay is proportional to the slow-start capacitor value and lasts until the ss/ena pin reaches the enable threshold. the start-up delay is approximately: (25) second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor. the slow-start time set by the capacitor is approximately: (26) the actual slow-start is likely to be less than the above approximation due to the brief ramp-up at the internal rate. vbias regulator (vbias) the vbias regulator provides internal analog and digital blocks with a stable supply voltage over variations in junction temperature and input voltage. a high quality, low-esr, ceramic bypass capacitor is required on the vbias pin. x7r or x5r grade dielectrics are recommended because their values are more stable over temperature. place the bypass capacitor close to the vbias pin and returned to agnd. external loading on vbias is allowed, with the caution that internal circuits require a minimum vbias of 2.70 v, and external loads on vbias with ac or digital switching noise may degrade performance. the vbias pin may be useful as a reference voltage for external circuits. voltage reference the voltage reference system produces a precise v ref signal by scaling the output of a temperature stable bandgap circuit. during manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 v at the output of the error amplifier, with the amplifier connected as a voltage follower. the trim procedure adds to the high precision regulation of the tps54110, since it cancels offset errors in the scale and error amplifier circuits. oscillator and pwm ramp the oscillator frequency can be set to internally fixed values of 350 khz or 550 khz using the sync pin as a static digital input. if a different frequency of operation is required for the application, the oscillator frequency can be externally adjusted from 280 khz to 700 khz by connecting a resistor from the rt pin to ground and floating the sync pin. the switching frequency is approximated by the following equation, where r is the resistance from rt to agnd: ? 2003 C 2011, texas instruments incorporated submit documentation feedback 19 product folder link(s): tps54110 d (ss) 1.2v t =c 5 a m (ss) (ss) 0.7v t =c 5 a m
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com (27) external synchronization of the pwm ramp is possible over the frequency range of 330 khz to 700 khz by driving a synchronization signal into sync and connecting a resistor from rt to agnd. choose an rt resistor that sets the free-running frequency to 80% of the synchronization signal. table 3 summarizes the frequency selection configurations. table 3. summary of the frequency selection configurations switching frequency sync pin rt pin 350 khz, internally set float or agnd float 550 khz, internally set 2.5 v float externally set 280 khz to 700 khz float r = 68 k to 180 k externally synchronized r = rt value for 80% of external synchronization signal frequency synchronization frequency error amplifier the high-performance, wide-bandwidth, voltage error amplifier sets the tps54110 apart from most dc/dc converters. the user is given the flexibility to use a wide range of output l- and c-filter components to suit the particular application needs. type-2 or type-3 compensation can be employed using external compensation components. pwm control signals from the error-amplifier output, oscillator, and current-limit circuit are processed by the pwm control logic. referring to the internal block diagram, the control logic includes the pwm comparator, or gate, pwm latch, and portions of the adaptive dead-time and control-logic block. during steady-state operation below the current-limit threshold, the pwm-comparator output and oscillator pulse train alternately reset and set the pwm latch. once the pwm latch is set, the low-side fet remains on for a minimum duration set by the oscillator pulse duration. during this period, the pwm ramp discharges rapidly to its valley voltage. when the ramp begins to charge back up, the low-side fet turns off and high-side fet turns on. as the pwm ramp voltage exceeds the error-amplifier output voltage, the pwm comparator resets the latch, thus turning off the high-side fet and turning on the low-side fet. the low-side fet remains on until the next oscillator pulse discharges the pwm ramp. during transient conditions, the error amplifier output could be below the pwm ramp valley voltage or above the pwm peak voltage. if the error-amplifier output is high, the pwm latch is never reset and the high-side fet remains on until the oscillator pulse signals the control logic to turn the high-side fet off and the low-side fet on. the device operates at its maximum duty cycle until the output voltage rises to the regulation set-point, setting vsense to approximately the same voltage as v ref . if the error-amplifier output is low, the pwm latch is continually reset and the high-side fet does not turn on. the low-side fet remains on until the vsense voltage decreases to a range that allows the pwm comparator to change states. the tps54110 is capable of sinking current continuously until the output reaches the regulation set-point. if the current-limit comparator remains tripped longer than 100 ns, the pwm latch resets before the pwm ramp exceeds the error-amplifier output. the high-side fet turns off and low-side fet turns on to decrease the energy in the output inductor, and consequently the output current. this process is repeated each cycle that the current-limit comparator is tripped. dead-time control and mosfet drivers adaptive dead-time control prevents shoot-through current from flowing in both n-channel power mosfets during the switching transitions by actively controlling the turn-on times of the mosfet drivers. the high-side driver does not turn on until the gate-drive voltage to the low-side fet is below 2 v. the low-side driver does not turn on until the voltage at the gate of the high-side mosfets is below 2 v. the high-side and low-side drivers are designed with 300-ma source and sink capability to quickly drive the power mosfets gates. the low-side driver is supplied from vin, while the high-side driver is supplied from the boot pin. a bootstrap circuit uses an external boot capacitor and an internal 2.5- bootstrap switch connected between the vin and boot pins. the integrated bootstrap switch improves drive efficiency and reduces external-component count. 20 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110 w 100k switching frequency= 500 khz r
tps54110 www.ti.com slvs500c C december 2003 C revised february 2011 overcurrent protection cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side mosfet and differential amplifier and comparing it to the preset overcurrent threshold. the high-side mosfet is turned off within 200 ns of reaching the current-limit threshold. a 100-ns leading-edge blanking circuit prevents false tripping of the current limit. current-limit detection occurs only when current flows from vin to ph when sourcing current to the output filter. load protection during current-sink operation is provided by thermal shutdown. thermal shutdown the device uses the thermal shutdown to turn off the power mosfets and disable the controller if the junction temperature exceeds 150 c. the device is released from shutdown when the junction temperature decreases to 10 c below the thermal-shutdown trip point, and starts up under control of the slow-start circuit. thermal shutdown provides protection when an overload condition is sustained for several milliseconds. in a persistent-fault condition, the device cycles continuously; starting up under control of the soft-start circuit, heating up due to the fault, and then shutting down upon reaching the thermal-shutdown point. power good (pwrdg) the power-good circuit monitors for undervoltage conditions on vsense. if the voltage on vsense is 7% below the reference voltage, the open-drain pwrgd output is pulled low. pwrgd is also pulled low if vin is less than the uvlo threshold, or ss/ena is low, or if thermal shutdown asserts. when vin = uvlo threshold, ss/ena = enable threshold, and vsense > 93% of v ref , the open-drain output of the pwrgd pin is high. a hysteresis voltage equal to 3% of v ref and a 35- s falling-edge deglitch circuit prevent tripping of the power-good comparator due to high frequency noise. pcb layout considerations the vin pins are connected together on the printed board (pcb) and bypassed with a low-esr ceramic bypass capacitor. minimize the loop area formed by the bypass capacitor connections, the vin pins, and the tps54110 ground pins. the recommended bypass capacitor is 10- f (minimum) ceramic with x5r or x7r dielectric. the optimum placement is closest to the vin pins and the agnd and pgnd pins. see figure 31 for an example layout. it has an area of ground on the top layer directly under the ic, with an exposed area for connection to the powerpad. use vias to connect this ground area to any internal ground planes. use additional vias at the ground side of the input and output filter capacitors as well. tie the agnd and pgnd pins to the pcb ground area under the device as shown. use a separate wide trace for the analog-ground path, connecting the voltage set-point divider, timing resistor rt, slow-start capacitor and bias-capacitor grounds. tie the ph pins together and route to the output inductor. since the ph connection is the switching node, locate the inductor very close to the ph pins, and minimize the area of the conductor to prevent excessive capacitive coupling. connect the boot capacitor between the phase node and the boot pin as shown. keep the boot capacitor close to the ic and minimize the conductor trace lengths. connect the output-filter capacitor(s) as shown between the vout trace and pgnd. it is important to keep the loop formed by the ph pins, lout, cout and pgnd as small as is practical. place the compensation components from the vout trace to the vsense and comp pins. do not place these components too close to the ph trace. due to the size of the ic package and the device pin-out, they must be somewhat closely routed while maintaining as much separation as possible, yet keeping the layout compact. connect the bias capacitor from the vbias pin to analog ground using the isolated analog ground trace. if a slow-start capacitor or rt resistor is used, or if the sync pin is used to select 350-khz operating frequency, connect them to this trace as well. ? 2003 C 2011, texas instruments incorporated submit documentation feedback 21 product folder link(s): tps54110
tps54110 slvs500c C december 2003 C revised february 2011 www.ti.com figure 31. pc board layout example 22 submit documentation feedback ? 2003 C 2011, texas instruments incorporated product folder link(s): tps54110 agnd boot vsense comppwrgd phph ph ph ph rt sync ss/ena vbias vin vin vin pgndpgnd pgnd vout ph vin topside ground area via to ground plane analog ground trace exposed powerpad area compensation network output inductor output filter capacitor boot capacitor input bypass capacitor inputbulk filter frequency set resistor slow start capacitor bias capacitor pgnd cout lout
package option addendum www.ti.com 8-nov-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps54110pwp active htssop pwp 20 70 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tps54110 tps54110pwpg4 active htssop pwp 20 70 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tps54110 tps54110pwpr active htssop pwp 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tps54110 tps54110pwprg4 active htssop pwp 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 85 tps54110 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 8-nov-2014 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of tps54110 : ? automotive: TPS54110-Q1 note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps54110pwpr htssop pwp 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 q1 package materials information www.ti.com 14-jul-2012 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps54110pwpr htssop pwp 20 2000 367.0 367.0 38.0 package materials information www.ti.com 14-jul-2012 pack materials-page 2

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